Senior Talent Acquisition at AIonSi
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AIonSi - Design Verification Engineer (0-3 yrs)
Requirement :
- Proficiency in Digital Electronics
- Expertise in Verilog and System Verilog (SV)
- Familiarity with Verification Methodologies such as UVM/OVM
- Proficient coding skills in Verilog and SV
- Strong analytical, problem-solving, and debugging abilities
- Effective communication and interpersonal skills
Qualification :
- Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering.
- Trained in VLSI Design & Verification
Experience : Fresher's - 3 years
Year of Graduation:
- B.E/B.TECH (2021 or older)
- M.E/ M.TECH (2023 or older)
