As a Design-for-Testability (DFT) Architect, the candidate is expected to have prior experience in defining the DFT Architecture, methodology flow and DFT implementation verification plan.

The candidate also should have DFT end to end execution experience from DFT spec definition to post silicon bringup.

The candidate will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion.

PREFERRED EXPERIENCE:

- DFT methodology/architecture and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, PHY loopback, etc)

- Siemens Tessent and/or Cadence Modus.

- Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design

- Prior experience and exposure to DFT timing closure is critical

- Pre-Silicon test planning & validation, engagement with design teams

- Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies

- Optimization of test flows for increased quality and cost improvement

- Analysis of part failures leading to test coverage and yield improvement

- Analysis of characterization data across PVT

- Must have good communication skills and the ability to work in a worldwide team environment

KEY RESPONSIBILITIES:

- Work with architecture team and production engineers to understand the product specification, DFT requirements, clock structure, power management and interconnect

- Define and drive DFT architecture and implementation plan for the project based on this knowledge

- Work with DFT execution team for Implementation and verification of DFT features

- Scan/JTAG/Boundary Scan insertion and ATPG pattern generation

- Memory BIST logic generation, implementation and verification

- SoC level ATPG pattern verification with gate level simulation

- Test coverage and test cost reduction analysis

- Familiar with DFT timing closure and ECO

- Post silicon support and debug to ensure successful bring-up and enhance yield learning

- Help scope and analyze new design opportunities

- Actively work on DFT methodology and process improvements

- Knowledge & experience of low power concepts, clock gating, power gating is a plus

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