Full Chip Clock Planning

Our client is engaged in VLSI services and turn key projects maintaining the core values of "Quality and Commitment"?. They specialise in Physical Design, Synthesis & STA, Flow Development, Low Power Designs, digital design, ASIC Design, FPGA Design, and RTL Design

They are looking for Full Chip Clock Planning to be based at Bengaluru with the following:

- Must have 5+ years of Clocking experience in end-to-end specification, planning, analyzing, and implementing clock distribution networks for complex designs in the latest process nodes while ensuring timing closure.

- Must have experience in Implementing End-to-End Clocking solutions for multi-core CPU with different designs like source synchronous, daisy chain, common clock etc

- Must be able to determine global clock topology, clock gate placement and LS placement. Simulate and provide final jitter values for STA.

- Must be able to provide the spec and built recipe for sub-system clock implementation to meet target clock insertion latencies

- Must be able to develop automation to analyze clock skew and generate clock push or pull for converging the data path

- Must be able to define clock methodology including clock structure, simulation model, and physical implementation for the SOC

- Must be able to develop and maintain clock tree synthesis flow

- Must be able to Analyze clock tree quality

- Must be able to engage with the SOC physical design team on the adoption of the clock methodology

- Education: PhD, Master s Degree or Bachelor s Degree in EE, EECS or CE with more than five years of experience in Chip Clock Planning

This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.