ASIC / VLSI Consultant at MY Search
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Full Chip Timing - STA Lead (6-20 yrs)
Our client is engaged in VLSI services and turn key projects maintaining the core values of "Quality and Commitment". They specialise in Physical Design, Synthesis & STA, Flow Development, Low Power Designs, digital design, ASIC Design, FPGA Design, and RTL Design
They are looking for Full Chip Timing - STA Lead to be based at Bengaluru with the following:
1. Must have 6+ years of experience STA with 1+ years of experience leading a team of STA engineers and close high frequency, lower tech node complex designs.
2. Must have experience in full chip timing analysis from early investigation to final implementation and tapeout.
3. Must have developed timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.
4. Must have hands-on experience working with architects and logic designers to generate block and full chip timing constraints.
5. Analyse scenarios and margin strategies with Synthesis & Design team.
6. Partner with physical design teams to close and sign off the designs through PnR and ECO cycles.
7. Must have hands-on experience in ASIC timing constraints generation and timing closure.
8. Expertise and advanced knowledge of industry standard timing EDA tools (Prime Time, StarRC etc.).
9. Deep understanding and experience in timing closure of various functional and test modes
10. Expertise in deep-sub micron processes (Crosstalk delay, noise glitch, POCV, IR-STA).
11. Proficient in scripting (TCL, Perl, Python, csh/bash).
12. Education: PhD, Masters or Bachelors Degree in EE, EECS or CS.
Kindly send your profile to tulsiarora(at)mysearch.in.net or call on 90361 39000 / 99451 75345
