ASIC / VLSI Consultant at MY Search
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Lead - Full Chip Floor Plan Engineer (5-20 yrs)
Full Chip Floor Plan Engineer / Lead
Our client is engaged in VLSI services and turn key projects maintaining the core values of "Quality and Commitment". They specialise in Physical Design, Synthesis & STA, Flow Development, Low Power Designs, digital design, ASIC Design, FPGA Design, and RTL Design
They are looking for Full Chip Floor Plan Engineer / Lead to be based at Bengaluru with the following:
1. Must have 5+ years of experience in full-chip physical design and layout for advanced process nodes (e.g., 7nm, 5nm).
2. Must have 5+ years of experience in creating an optimal floor plan for the chip, considering factors such as performance, power consumption, and area efficiency.
3. Must have experience with physical verification methodologies, including DRC, LVS, and ERC.
4. Strong understanding of semiconductor device physics, CMOS technology, and VLSI design principles.
5. Proficiency in industry-standard EDA tools for floor planning, such as Synopsys ICC/FC or equivalent.
6. Experience with scripting languages such as Tcl, Python, or Perl for automation tasks.
7. Familiarity with physical design methodologies, including hierarchical design, Pin planning, Chip Tile PnR.
8. Must have experience working closely with various teams, including design, architecture, and verification, to ensure the successful implementation of the chip design.
9. Education: Bachelor's or Master's degree in Electrical & Electronics Engineering or related field.
Kindly send your profile or call on 90361 39000 / 99451 75345
