Senior Executive at Sarvajith Infotech
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Physical Design Engineer - Semiconductor/Electronics (5-10 yrs)
1. Experience in Block/SOC level PD Implementation flow.
2. Netlist to GDSII / PD / Implementation flow / PnR / APR
3. Low power design experience
4. Floorplanning, Power planning, Placement, CTS, Routing, Extraction, DFM
5. Congestion and timing analysis, Coming with better QoR
Sign-off flow : STA, DRC/LVS/Antenna/ERC, Power analysis, IR/EM analysis, LEC, ECO (Timing and Functional)
6. Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing and Sign Off (STA, PV, IR/EM)
7. Experience in ECO implementation
8. Hands on experience in PnR tools Synopsys ICC II/ Cadence Innovus etc
9. Scripting skills: Perl, TCL . EDA Tools
10. Expectations from the Role
11. Excellent debugging and problem-solving skills
12. Effective communication skills to interact with all stakeholders
13. Must be highly focused and remain committed to obtaining closure on project goals.
14. Ability to work independently and complete work assigned
15. Should possess good Leadership Skills
16. Should have a Go-getter attitude
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