Lead-Talent Acquisition at Vipsa Talent Solutions
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RTL Verification Engineer (6-12 yrs)
- Lead and execute RTL verification tasks for IPs like UCIe, HBM, PCIe, and Bus Logic.
- Implement advanced verification methodologies such as UVM/OVM/VMM/SystemVerilog.
- Generate constrained random stimulus and perform assertion-based verification and functional coverage.
- Oversee register verification standards and manage NLP/GLS verification flows.
- Conduct IP and sub-system level verification for protocols including PCIe, UCIe, and HBM.
- Facilitate controller interoperability testing at the sub-system level.
Qualifications:
- BE/ME/MTech/MS in Electrical Engineering or a related field.
- 6 to 12 years of RTL verification experience.
- Proficiency in UVM/OVM/VMM/System Verilog.
- Strong knowledge of constrained random stimulus generation, assertion-based verification, and functional coverage techniques.
- Experience with register verification standards and NLP/GLS verification flows.
- Hands-on experience in IP and sub-system level verification for protocols like PCIe, UCIe, and HBM is a strong plus.
- Prior experience in controller interoperability testing at the sub-system level is desirable.
